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Design Verification Engineer, Silicon

Google organizes the world's information and makes it universally accessible and useful, combining AI, Software, and Hardware to create radically helpful experiences.
Backend
Mid-Level Software Engineer
In-Person
5,000+ Employees
4+ years of experience
Enterprise SaaS

Description For Design Verification Engineer, Silicon

Google is seeking a Design Verification Engineer to join their Silicon team in Bengaluru. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position combines hardware engineering with software verification, requiring expertise in SystemVerilog and UVM methodologies.

The ideal candidate will work on verification of high-speed IOs, IP/subsystem functional verification, and chips pervasive IP. They will be responsible for creating and maintaining complex verification environments, developing cross-language tools, and ensuring comprehensive test coverage.

This is an exciting opportunity to work at one of the world's leading technology companies, contributing to products used by millions globally. The role offers the chance to work with cutting-edge technology and shape the next generation of hardware experiences.

Google offers a collaborative environment focused on innovation and technical excellence. The company is committed to diversity and inclusion, providing equal opportunities for all qualified candidates. The position requires a strong technical background in verification methodologies and a passion for developing robust testing environments.

Working at Google means being part of a team that pushes boundaries in hardware development, delivering unparalleled performance, efficiency, and integration. The role combines technical challenges with the opportunity to impact Google's hardware ecosystem directly.

Last updated 3 days ago

Responsibilities For Design Verification Engineer, Silicon

  • Plan and execute the verification of high speed Inputs/Outputs (IOs)
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM
  • Create and maintain verification environments using SystemVerilog, Universal Verification Methodology (UVM)
  • Develop cross language tools and verification methodologies
  • Identify and write all types of coverage measures for stimulus and corner-cases

Requirements For Design Verification Engineer, Silicon

Java
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
  • 4 years of experience with verification methodologies and languages such as UVM and SystemVerilog
  • Experience developing and maintaining verification testbenches, test cases, and test environments

Benefits For Design Verification Engineer, Silicon

Medical Insurance
Vision Insurance
Dental Insurance
  • Health insurance
  • Vision coverage
  • Dental coverage
  • Equal opportunity employer

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