Full Chip Physical Integration and CAD Engineer, Silicon

Join Google's innovative hardware team as a Full Chip Physical Integration and CAD Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced ASIC physical design with mixed-signal expertise, requiring deep technical knowledge in RTL2GDS flows and physical design integration.

As part of Google's mission to organize the world's information and make it universally accessible, you'll work with a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. The position involves developing and implementing sophisticated physical design methodologies, managing complex timing and power convergence, and driving innovation in Performance, Power, and Area optimization.

The ideal candidate brings 10+ years of experience in ASIC physical design flows and methodologies in advanced process nodes, with strong expertise in synthesis, Place and Route (PnR), and sign-off convergence. You'll be responsible for complete ownership of physical design integration and CAD flow for Mixed signal chip development, contributing directly to products used by millions worldwide.

This role offers the opportunity to shape the next generation of hardware experiences at Google, working with cutting-edge technology and collaborating with world-class engineers. You'll be instrumental in delivering unparalleled performance, efficiency, and integration in Google's hardware products, while being part of a company culture that values innovation, technical excellence, and inclusive design.

The position is based in Bengaluru, Karnataka, India, where you'll have access to Google's state-of-the-art facilities and resources. Join a team that's pushing the boundaries of what's possible in custom silicon design and be part of creating the future of Google's hardware ecosystem.