Multimedia Core IP RTL Design Engineer, Silicon
Description For Multimedia Core IP RTL Design Engineer, Silicon
Join Google's gChips team in developing custom silicon solutions that power the future of Google's direct-to-consumer products. As a Multimedia Core IP RTL Design Engineer, you'll be part of a team that designs interconnect IP for Pixel System on a Chip (SoCs). The role involves collaborating with architecture, software, verification, power, and timing teams to deliver high-quality Register-Transfer Level (RTL) designs.
The position requires expertise in RTL coding, microarchitecture development, and implementation of multimedia processing blocks. You'll work on solving technical challenges related to power, performance, and area optimization while ensuring design quality through various methodologies including Lint, CDC, and RDC checks.
Google's gChips team focuses on developing custom silicon solutions that provide differentiated user experiences in Google Hardware products. The team works on SoCs and other mixed signal, logic, and sensor ICs, mapping out silicon requirements 2-4 years ahead. This role offers the opportunity to shape the next generation of hardware experiences, delivering unparalleled performance and efficiency.
The ideal candidate will have strong experience in RTL design, computer architecture, and multimedia IP implementation. You'll be working in a collaborative environment, contributing to Google's mission of organizing world's information and making it universally accessible through innovative hardware solutions.
Working at Google means joining a team that combines the best of Google AI, Software, and Hardware to create radically helpful experiences. The company offers a supportive environment focused on technical excellence and innovation, with opportunities to work on cutting-edge silicon technology that impacts millions of users worldwide.
Responsibilities For Multimedia Core IP RTL Design Engineer, Silicon
- Collaborate with architects and develop microarchitecture
- Perform Verilog/SystemVerilog RTL coding, functional/performance simulation debug and Lint/CDC/FV/UPF checks
- Develop RTL implementations that meet engaged power, performance and area goals
- Participate in synthesis, timing/power closure and support pre-silicon and post-silicon bring-up
- Travel to other sites across the world to collaborate with global teams
Requirements For Multimedia Core IP RTL Design Engineer, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, or equivalent practical experience
- 4 years of experience in RTL coding
- Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC)
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