Physical Design and Timing Engineer, Signoff Methodology
Description For Physical Design and Timing Engineer, Signoff Methodology
Join Google's innovative hardware team as a Physical Design and Timing Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines the best of Google's AI, Software, and Hardware capabilities to create groundbreaking experiences used by millions worldwide.
As a Physical Design and Timing Engineer, you'll be responsible for driving methodologies for mobile System on Chips (SoC), focusing on optimizing Power Performance Area (PPA) and yield. You'll work with cutting-edge technology and collaborate with cross-functional teams including architecture, IPs, design, foundry, CAD, and sign-off methodology teams.
The position requires expertise in timing analysis, physical design, and scripting languages, making it perfect for someone who enjoys working at the intersection of hardware and software. You'll be part of Google's mission to organize the world's information and make it universally accessible and useful through innovative hardware solutions.
The role offers the opportunity to work on challenging technical problems while contributing to products that make a real difference in people's lives. You'll be based in Bengaluru, working with a global team of experts in a company known for its technical excellence and innovative culture.
This is an excellent opportunity for an experienced engineer looking to make a significant impact in the field of silicon design and timing methodology, while working on products that push the boundaries of what's possible in consumer hardware.
Responsibilities For Physical Design and Timing Engineer, Signoff Methodology
- Drive the physical design and sign-off timing methodologies for mobile System on a Chips (SoC) to push Power Performance Area (PPA) and yield
- Analyze power performance area trade-offs across different methodologies and technologies
- Work with cross-functional architecture, IPs, design, foundry, CAD and sign-off methodology teams
Requirements For Physical Design and Timing Engineer, Signoff Methodology
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience in timing analysis and physical design
- Experience in one or more scripting languages, such as Perl, TCL, Python
Benefits For Physical Design and Timing Engineer, Signoff Methodology
- Comprehensive health benefits including medical, dental, and vision coverage
- Parental leave benefits
- Equal employment opportunity
