Physical Design and Timing Engineer, Signoff Methodology
Description For Physical Design and Timing Engineer, Signoff Methodology
Google is seeking a Physical Design and Timing Engineer to join their hardware team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware engineering expertise with software development, working on mobile System on Chips (SoC) to optimize Power Performance Area (PPA) and yield.
The position requires strong technical skills in timing analysis, physical design, and scripting languages like Python, Perl, or TCL. You'll be working at the intersection of hardware and software, driving methodologies that shape the next generation of Google's hardware experiences. The role involves close collaboration with cross-functional teams including architecture, IPs, design, foundry, CAD, and sign-off methodology teams.
As part of Google's mission to organize the world's information and make it universally accessible, you'll contribute to creating radically helpful experiences by combining Google's AI, Software, and Hardware capabilities. The team focuses on researching, designing, and developing new technologies to make computing faster, seamless, and more powerful.
This is an excellent opportunity for someone with a strong background in physical design and timing analysis who wants to work on cutting-edge hardware projects at scale. The role offers the chance to directly impact millions of users worldwide through Google's consumer products while working with state-of-the-art technology and methodologies.
Responsibilities For Physical Design and Timing Engineer, Signoff Methodology
- Drive the physical design and sign-off timing methodologies for mobile System on a Chips (SoC) to push Power Performance Area (PPA) and yield
- Analyze power performance area trade-offs across different methodologies and technologies
- Work with cross-functional architecture, IPs, design, foundry, CAD and sign-off methodology teams
Requirements For Physical Design and Timing Engineer, Signoff Methodology
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience in timing analysis and physical design
- Experience in one or more scripting languages, such as Perl, TCL, Python
- Experience in physical design tool automation (synthesis, PandR) preferred
- Experience in extraction of design parameters, QoR metrics and analyzing data trends preferred
- Experience in engineering across physical design and level implementation preferred
- Knowledge of parasitic extraction tools and flow preferred
- Knowledge of timing signoff conditions and parameters preferred
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