RTL Design Engineer, Core-IP
Description For RTL Design Engineer, Core-IP
Google is seeking an RTL Design Engineer to join their Core-IP team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware innovation with Google's expertise in AI and software to create transformative computing experiences.
The position involves RTL design development of audio and Security IPs and subsystems, requiring expertise in microarchitecture, RTL coding, low power design, and various optimization techniques. You'll be responsible for developing implementations that meet competitive power, performance, and area targets while ensuring high-quality security designs.
As part of Google's hardware team, you'll contribute to technologies that make computing faster, seamless, and more powerful. The role requires collaboration with architects, participation in test planning, and support for both pre-silicon and post-silicon bring-up phases. Your work will directly impact millions of users worldwide through Google's hardware products.
The ideal candidate should have strong experience in ASIC design methodologies, SystemVerilog RTL design, and scripting capabilities. This position offers the opportunity to work on cutting-edge hardware development while being part of Google's mission to organize the world's information and make it universally accessible and useful.
This role combines technical expertise with collaborative teamwork, offering the chance to shape the future of Google's hardware experiences while working with state-of-the-art technology and talented professionals in the field.
Responsibilities For RTL Design Engineer, Core-IP
- Collaborate with architects and develop microarchitecture
- Perform Verilog/SystemVerilog RTL coding, functional/performance simulation debug and Lint/CDC/FV/UPF checks
- Develop RTL implementations that meet competitive power, performance and area targets
- Participate in synthesis, timing/power closure, and support pre-silicon and post-silicon bring-up
- Participate in test planning and coverage analysis. Create tools/scripts to automate tasks and track progress
Requirements For RTL Design Engineer, Core-IP
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience
- 3 years of experience designing RTL digital logic using SystemVerilog for ASICs or equivalent experience
- Experience with ASIC design methodologies and QA flows (Lint, CDC, RDC, VCLP)
- Experience with a scripting language such as Perl or Python
Jobs Related To Google RTL Design Engineer, Core-IP
