Senior ASIC Design Verification Engineer, TPU Compute
Description For Senior ASIC Design Verification Engineer, TPU Compute
Google is seeking a Senior ASIC Design Verification Engineer to join their ML, Systems, & Cloud AI (MSCA) organization, focusing on TPU (Tensor Processing Unit) technology. This role offers an exciting opportunity to shape the future of AI/ML hardware acceleration at one of the world's leading tech companies.
The position involves working on cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You'll be part of a team developing custom silicon solutions that drive the future of Google's TPU architecture. Your responsibilities will include verifying complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
The MSCA organization is responsible for designing, implementing, and managing the hardware, software, machine learning, and systems infrastructure for all Google services (including Search and YouTube) and Google Cloud. The team prioritizes security, efficiency, and reliability across all aspects of their work, from TPU development to global network management.
This role requires strong expertise in ASIC design verification, with particular emphasis on SystemVerilog and UVM. You'll be responsible for creating verification environments, debugging tests, and ensuring functional correctness of design blocks. The position offers competitive compensation, including a base salary range of $156,000-$229,000, plus bonus, equity, and comprehensive benefits.
The ideal candidate will have at least 7 years of experience with industry-standard tools and methodologies for IC development, along with strong skills in SystemVerilog. Additional expertise in memory subsystem design verification, power-aware verification, and post-silicon bring-up would be advantageous.
This is an excellent opportunity for an experienced verification engineer to work on groundbreaking AI hardware technology while contributing to products used by billions of people worldwide. The role offers the chance to work with cutting-edge technology in a collaborative environment while helping shape the future of AI acceleration hardware.
Responsibilities For Senior ASIC Design Verification Engineer, TPU Compute
- Plan the verification of complex digital design blocks by fully understanding the design specification and interact with design engineers to identify important verification scenarios
- Create a constrained-random verification environment using SystemVerilog and UVM
- Identify and write different types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Execute the closure of coverage measures, identification of verification holes, and demonstration of progress towards tape-out
Requirements For Senior ASIC Design Verification Engineer, TPU Compute
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 7 years of experience with industry standard tools, languages and methodologies relevant to the development of silicon-based ICs and chips
- Experience with SystemVerilog (i.e. SystemVerilog Assertions or functional coverage)
Benefits For Senior ASIC Design Verification Engineer, TPU Compute
- Medical Insurance
- Equity
- 401k
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