Senior Design Engineer, Silicon
Description For Senior Design Engineer, Silicon
Google is seeking a Senior Design Engineer to join their Silicon team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware engineering with Google's cutting-edge AI and software capabilities to create innovative computing solutions. The position requires expertise in RTL design, microarchitecture, and low-power optimization.
The ideal candidate will work on defining and implementing complex microarchitectural features, handling RTL development using SystemVerilog, and ensuring quality through various verification processes. This role is crucial in Google's mission to create faster, more efficient computing experiences that impact millions of users worldwide.
The position offers the opportunity to work with a diverse team at one of the world's leading technology companies, contributing to next-generation hardware experiences. Located in Bengaluru, the role requires strong technical skills in hardware design and verification, combined with programming capabilities in Perl or Python.
This is an excellent opportunity for experienced hardware engineers looking to make a significant impact on Google's hardware infrastructure and consumer products. The role combines technical depth with the scale and resources of Google, offering the chance to work on cutting-edge silicon solutions that will shape the future of computing technology.
Responsibilities For Senior Design Engineer, Silicon
- Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
- Perform Register-Transfer Level (RTL) development (SystemVerilog), RTL integration (Perl), debug functional/performance simulations
- Perform RTL quality checks including Lint, CDC, RDC, Synthesis, Unified Power Format (UPF) checks
Requirements For Senior Design Engineer, Silicon
- Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience
- 3 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture
- Experience in handling low power schemes, power roll up and power estimations
- Experience in Register-Transfer Level (RTL) quality sign-off flows (e.g., CDC, RDC, Lint, Power Intent or LEC)
- Experience with Perl or Python
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