Senior DFT Engineer, Google Cloud
Description For Senior DFT Engineer, Google Cloud
Join Google Cloud's Technical Infrastructure team as a Senior DFT Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role focuses on defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital and mixed-signal chips. You'll be responsible for creating silicon test strategies, DFT architecture, and specifications for next-generation SoCs.
The position involves working with cutting-edge technology in Google's Technical Infrastructure team, which is fundamental to keeping Google's vast product portfolio running smoothly. You'll be part of the team that develops and maintains data centers and builds next-generation Google platforms, ensuring networks operate at peak performance to deliver the best user experience.
Your responsibilities will span from pre-silicon verification to post-silicon testing, working closely with test engineers to reduce test costs, increase production quality, and enhance yield. The role requires expertise in DFT logic insertion, MBIST implementation, and comprehensive documentation of test architectures.
This is an excellent opportunity for experienced engineers who want to impact millions of users worldwide through Google's hardware innovations. You'll be working in Bengaluru, India, contributing to Google's mission of developing unparalleled performance, efficiency, and integration in their hardware products.
The position offers the chance to work with state-of-the-art EDA tools and be part of a team that pushes the boundaries of silicon technology. Your work will directly influence the quality and reliability of Google's hardware products, making this an impactful role for those passionate about hardware testing and validation.
Responsibilities For Senior DFT Engineer, Google Cloud
- Develop DFT strategy and architecture, including hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO
- Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic
- Document DFT architecture and test sequences, including boot-up sequence associated with test pins
- Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations
Requirements For Senior DFT Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience
- 5 years of experience in DFT specification definition architecture and insertion
- 3 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent)
- Experience with ASIC DFT synthesis, STA, simulation, and verification flow
- Experience working with ATE engineers
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