Senior IP Design Verification Engineer, Silicon
Description For Senior IP Design Verification Engineer, Silicon
Join Google's Silicon team as a Senior IP Design Verification Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines the best of Google's AI, Software, and Hardware capabilities to create groundbreaking technological experiences. You'll be responsible for verifying next-generation configurable Infrastructure IPs, interconnects, and memory subsystems, working with cutting-edge verification methodologies including SystemVerilog and UVM.
The position requires strong expertise in digital system verification, particularly with standard IP components and interconnects. You'll be creating and enhancing constrained-random verification environments, writing comprehensive coverage measures, and collaborating closely with design engineers to ensure functional correctness of blocks and subsystems. The role demands both technical depth in verification methodologies and the ability to drive projects toward tape-out completion.
As part of Google's hardware team, you'll contribute to innovations that impact millions of users worldwide. The team's mission focuses on making computing faster, seamless, and more powerful, ultimately aiming to improve people's lives through technology. This is an excellent opportunity for experienced verification engineers who want to work on challenging projects at scale, with access to Google's vast resources and innovative technology stack.
The role offers the chance to work in Bengaluru, India, collaborating with global teams on critical hardware infrastructure projects. You'll be part of Google's larger mission to organize the world's information while working on tangible products that showcase the company's technical excellence in hardware design and verification.
Responsibilities For Senior IP Design Verification Engineer, Silicon
- Plan and execute the verification of the next generation configurable Infrastructure Intellectual Property (IPs), interconnects and memory subsystems
- Create and enhance constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM)
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct blocks and subsystems
- Close coverage measures to identify verification holes and to show progress towards tape-out
Requirements For Senior IP Design Verification Engineer, Silicon
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience with Intellectual Property (IP) Development or Integration
- Experience in verifying digital systems using standard IP components or interconnects
- Experience creating and using verification components and environments in UVM
- Experience verifying digital logic at RTL level using SystemVerilog or C/C++
- Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL)
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