Senior RTL Design Engineer, Core IP, Silicon
Description For Senior RTL Design Engineer, Core IP, Silicon
Google is seeking a Senior RTL Design Engineer to join their Devices & Services team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware engineering expertise with Google's mission to organize the world's information and make it universally accessible.
The position requires deep expertise in RTL design, with responsibilities including microarchitecture definition, RTL implementation, and system integration. You'll be working on cutting-edge hardware designs that require optimizing for power, performance, and area while ensuring robust functionality through various verification methods.
As a senior engineer, you'll be involved in all aspects of the design process, from architecture planning to silicon bring-up. The role demands both technical excellence in hardware design and the ability to collaborate with multi-disciplinary teams across different locations. You'll be contributing to innovations that directly impact millions of users worldwide through Google's hardware products.
The ideal candidate should have at least 10 years of RTL design experience, with a strong background in ASIC design methodologies. Knowledge of System Verilog/Verilog is essential, and experience with machine learning accelerators, camera ISP image processing, or multimedia IPs would be highly valuable. The position offers the opportunity to work on next-generation hardware experiences, pushing the boundaries of performance, efficiency, and integration.
This role is based in Bangalore, India, and offers the chance to work with Google's world-class engineering teams while contributing to products that combine the best of Google AI, Software, and Hardware. The position requires a bachelor's degree in Electrical Engineering or Computer Science, though advanced degrees are preferred.
Responsibilities For Senior RTL Design Engineer, Core IP, Silicon
- Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top-level integration
- Define and develop RTL implementations that meet engaged power, performance and area goals
- Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in test plan and coverage analysis of the sub-system and chip-level verification
- Create tools/scripts to automate tasks and track progress
- Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning
Requirements For Senior RTL Design Engineer, Core IP, Silicon
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
- 10 years of work experience in RTL design
- Experience with ASIC design methodologies for clock domain checks and reset checks
- Experience in RTL coding using System Verilog/Verilog
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