Senior RTL Design Engineer, Core IP, Silicon
Description For Senior RTL Design Engineer, Core IP, Silicon
Google is seeking a Senior RTL Design Engineer to join their Devices & Services team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware expertise with Google's AI and software capabilities to create innovative user experiences. The position requires deep expertise in RTL design and ASIC methodologies, with responsibilities spanning from microarchitecture definition to implementation and verification.
The ideal candidate will have extensive experience in RTL design, with the ability to optimize for power, performance, and area goals. They will work on cutting-edge hardware designs that directly impact Google's product ecosystem, contributing to the development of next-generation hardware experiences that serve millions of users worldwide.
This role offers the opportunity to work with advanced technologies and multi-disciplinary teams, participating in all aspects of the design process from architecture planning to silicon bring-up. The position requires both technical expertise and collaborative skills, as the engineer will interact with various teams across RTL design, verification, and architecture planning.
Working at Google's Devices & Services team means being part of a mission to organize the world's information and make it universally accessible and useful through hardware innovation. The team focuses on creating radically helpful experiences by combining Google's AI, Software, and Hardware capabilities. This role is perfect for someone passionate about pushing the boundaries of hardware design and wanting to make a significant impact on products used by millions of people globally.
Responsibilities For Senior RTL Design Engineer, Core IP, Silicon
- Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top-level integration
- Define and develop RTL implementations that meet engaged power, performance and area goals
- Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in test plan and coverage analysis of the sub-system and chip-level verification
- Create tools/scripts to automate tasks and track progress
- Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning
Requirements For Senior RTL Design Engineer, Core IP, Silicon
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
- 10 years of work experience in RTL design
- Experience with ASIC design methodologies for clock domain checks and reset checks
- Experience in RTL coding using System Verilog/Verilog
Jobs Related To Google Senior RTL Design Engineer, Core IP, Silicon
