Senior SOC and IP Design Engineer, Google Cloud
Description For Senior SOC and IP Design Engineer, Google Cloud
Join Google Cloud's ML, Systems, & Cloud AI (MSCA) organization as a Senior SOC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware expertise with cutting-edge technology, focusing on designing and implementing critical infrastructure for Google services and Cloud operations.
As a Senior SOC and IP Design Engineer, you'll work on sophisticated Register-Transfer Level (RTL) development, utilizing languages like Verilog and System Verilog. Your responsibilities will span from defining SoC/block level design documents to participating in synthesis and silicon bring-up. The position requires strong technical skills in digital logic design, verification, and optimization techniques.
The role offers the opportunity to work with state-of-the-art technology in a global environment, contributing to systems that serve billions of users worldwide. You'll be part of a team that prioritizes security, efficiency, and reliability while pushing the boundaries of hyperscale computing. The position involves collaboration with multi-disciplined teams across different locations, making it ideal for someone who excels in both technical expertise and cross-functional communication.
This is an excellent opportunity for experienced engineers who want to make a significant impact on Google's hardware infrastructure while working with cutting-edge technology in areas like TPUs and global networking. The role combines challenging technical work with the chance to influence the future of Google's hardware experiences, making it perfect for those seeking to advance their career in silicon design at a leading tech company.
Responsibilities For Senior SOC and IP Design Engineer, Google Cloud
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks
- Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC-level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SOC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
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