Senior SOC and IP Design Engineer, Google Cloud
Description For Senior SOC and IP Design Engineer, Google Cloud
Join Google Cloud's innovative hardware team as a Senior SOC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's future direct-to-consumer products. As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll work on critical hardware infrastructure that supports Google's services and Cloud platform, including Search, YouTube, and Vertex AI.
Your role will involve sophisticated SOC and IP design, working with cutting-edge technologies in digital logic design, RTL development, and hardware verification. You'll be responsible for defining system architecture, implementing complex digital circuits, and ensuring optimal performance through various stages of the design process, from conception to silicon bring-up.
This position offers the opportunity to work with world-class engineers in a collaborative environment, contributing to projects that impact billions of users worldwide. You'll be involved in the complete design cycle, from architectural definition to silicon validation, utilizing your expertise in Verilog, System Verilog, and various hardware design methodologies.
The role combines technical depth in hardware design with the scale and impact of Google's infrastructure, making it an ideal position for experienced engineers looking to push the boundaries of custom silicon development. You'll be working in either Tel Aviv or Haifa, Israel, joining a team that prioritizes security, efficiency, and reliability in everything they do.
Working at Google means being part of a company that values innovation, technical excellence, and equal opportunity. You'll have access to cutting-edge tools and technologies, while contributing to products that shape the future of computing and artificial intelligence.
Responsibilities For Senior SOC and IP Design Engineer, Google Cloud
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks
- Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC-level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SOC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
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