Senior SOC RTL Design Engineer, Google Cloud
Description For Senior SOC RTL Design Engineer, Google Cloud
Join Google Cloud's ML, Systems, & Cloud AI (MSCA) organization as a Senior SOC RTL Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware expertise with cutting-edge technology development, focusing on designing and implementing critical infrastructure for Google services and Cloud operations.
As a Senior SOC RTL Design Engineer, you'll work on sophisticated System-on-Chip architectures, utilizing your extensive experience in digital logic design and RTL concepts. You'll be responsible for developing and optimizing hardware solutions that ensure high performance, efficiency, and reliability across Google's vast infrastructure. The position requires expertise in Verilog/SystemVerilog, PCIe protocols, and logic synthesis techniques.
The role offers the opportunity to work with state-of-the-art technology in a collaborative environment, contributing to projects that impact billions of users worldwide. You'll be part of a team that prioritizes security, efficiency, and reliability while pushing the boundaries of hyperscale computing. The position involves working with multi-disciplined teams across different locations, particularly in Tel Aviv and Haifa, Israel.
This is an excellent opportunity for experienced hardware engineers who want to make a significant impact on Google's infrastructure and cloud services. You'll be working on projects that directly influence the future of Google's hardware experiences, from TPUs to global network infrastructure, while contributing to the development of leading AI platforms like Vertex AI.
The role combines technical expertise with collaborative teamwork, requiring both deep technical knowledge and strong communication skills. You'll be part of Google's commitment to innovation in custom silicon solutions, working on projects that require sophisticated understanding of hardware design principles and modern computing architecture.
Responsibilities For Senior SOC RTL Design Engineer, Google Cloud
- Define the SOC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and ASIC silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For Senior SOC RTL Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Science, a related technical field, or equivalent practical experience
- 8 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
- Experience with PCIe (PCI)
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