Senior Staff CPU RTL Design Engineer
Description For Senior Staff CPU RTL Design Engineer
Join Google's innovative hardware team as a Senior Staff CPU RTL Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role offers an exciting opportunity to shape the next generation of hardware experiences, working on CPU subsystem development with a focus on microarchitecture and RTL design.
You'll be responsible for developing front-end designs for CPU subsystems, proposing and implementing performance-enhancing microarchitecture features, and collaborating with cross-functional teams including Software, Architect, and Performance teams. Your expertise in digital logic design and RTL concepts will be crucial in delivering designs that meet Performance Power Area (PPA) goals while maintaining production quality.
The position requires a deep understanding of CPU architecture, RTL design, and modern processor components. You'll work closely with verification teams to ensure design quality and with physical design teams to optimize frequency, power, and area goals. This is an opportunity to contribute to products used by millions worldwide while pushing the boundaries of hardware innovation.
The ideal candidate brings a master's degree in a relevant field, extensive experience with digital logic design principles, and proven expertise with RTL languages like SystemVerilog. You'll be part of a team that values technical excellence, innovation, and collaboration, working in an environment that encourages pushing boundaries and developing cutting-edge solutions.
Join Google's hardware team to be part of a company that's committed to technological advancement and creating products that make a difference. You'll have the opportunity to work with industry-leading experts, access to state-of-the-art resources, and the chance to shape the future of Google's hardware experiences.
Responsibilities For Senior Staff CPU RTL Design Engineer
- Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing on microarchitecture and RTL design for the next generation CPU
- Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies
- Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting Performance Power Area(PPA) goals with production quality
- Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals
- Become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation effort
Requirements For Senior Staff CPU RTL Design Engineer
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 10 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog
- Experience with RTL language (System Verilog) and related design processes (e.g., Lint, UPF)
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