Join Google's CoreIP Hardware Architecture team as a Senior Tensor Processing Unit Architect, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role combines advanced hardware architecture with machine learning acceleration, focusing on TPU (Tensor Processing Unit) development. You'll work on architecture specifications, performance optimization, and cross-functional collaboration with various teams including SoC architecture, IP design, and software development.
The position requires deep expertise in computer architecture and silicon design, with a focus on machine learning accelerators. You'll be responsible for optimizing Performance, Power, and Area (PPA) based on machine learning workload analysis, and defining hardware IP architecture specifications that meet critical product goals. The role involves close collaboration with algorithm teams, power and performance teams, and hardware IP design teams.
As part of Google's mission to organize the world's information, you'll contribute to creating radically helpful experiences by combining Google's AI, Software, and Hardware capabilities. The team focuses on making computing faster, seamless, and more powerful, ultimately aiming to improve people's lives through technology. This is an opportunity to shape the future of Google's hardware experiences and drive innovation in silicon technology.
The ideal candidate will bring a strong background in TPU or parallel processor architecture, demonstrated experience in micro-architecture optimization, and expertise in machine learning workload analysis. You'll be working in New Taipei City, Taiwan, contributing to Google's next generation of hardware products that are used by millions worldwide.