Silicon Design Verification Engineer, TPU, Google Cloud
Description For Silicon Design Verification Engineer, TPU, Google Cloud
Join Google's ML, Systems, & Cloud AI (MSCA) organization as a Silicon Design Verification Engineer working on TPU (Tensor Processing Unit) technology. In this role, you'll be at the forefront of AI/ML hardware acceleration, verifying complex digital designs that power Google's most demanding AI/ML applications. You'll own the full verification lifecycle, from planning to coverage closure, focusing on meeting stringent AI/ML performance and accuracy goals. The position involves building constrained-random verification environments, collaborating with design engineers, and ensuring reliability of AI/ML workloads on TPU hardware.
The role is part of Google's broader initiative in shaping the future of hyperscale computing, where you'll contribute to the development of custom silicon solutions that power Google's TPU architecture. You'll work with a diverse team that pushes boundaries and develops technology used by billions of people worldwide. The MSCA organization is responsible for the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud, including breakthrough technologies like Google Cloud's Vertex AI platform.
As a verification engineer, you'll apply your expertise in SystemVerilog, SVA, and UVM to create robust verification environments. You'll work closely with design teams to identify critical verification scenarios, implement comprehensive coverage metrics, and ensure the functional correctness of complex digital blocks. This position offers the opportunity to work on cutting-edge AI accelerator technology while contributing to Google's mission of advancing AI/ML capabilities through custom hardware solutions.
Responsibilities For Silicon Design Verification Engineer, TPU, Google Cloud
- Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Measure to identify verification holes and to show progress towards tape-out
- Create a constrained-random verification environment using SystemVerilog and Universal verification methodology (UVM)
Requirements For Silicon Design Verification Engineer, TPU, Google Cloud
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 4 years of experience with verification methodology such as Universal verification methodology (UVM)
- 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
- Experience with SystemVerilog, SVA, and functional coverage
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