Silicon Design Verification Engineer, TPU, Google Cloud
Description For Silicon Design Verification Engineer, TPU, Google Cloud
Join Google's ML, Systems, & Cloud AI (MSCA) organization as a Silicon Design Verification Engineer working on TPU (Tensor Processing Unit) technology. In this role, you'll be at the forefront of AI/ML hardware acceleration, verifying complex digital designs that power Google's most demanding AI/ML applications. You'll own the full verification lifecycle, from planning to coverage closure, focusing on meeting stringent AI/ML performance and accuracy goals.
The position involves building constrained-random verification environments to ensure reliability of AI/ML workloads on TPU hardware. You'll collaborate with design and verification engineers, working on active projects that shape the future of Google's custom silicon solutions. The role is critical in developing and verifying TPU architecture that integrates within AI/ML-driven systems.
As part of the MSCA organization, you'll contribute to the infrastructure that supports all Google services and Google Cloud. The team prioritizes security, efficiency, and reliability while driving towards the future of hyperscale computing. Your work will have global impact, supporting platforms like Google Cloud's Vertex AI and enabling Gemini models for enterprise customers.
This is an excellent opportunity for someone with strong verification methodology experience and interest in AI/ML hardware acceleration. You'll work with cutting-edge technology while contributing to products used by billions of people worldwide. The role offers the chance to work with industry-leading tools and methodologies while solving complex technical challenges in AI acceleration.
Responsibilities For Silicon Design Verification Engineer, TPU, Google Cloud
- Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios
- Identify and write all types of coverage measures for stimulus and corner-cases
- Debug tests with design engineers to deliver functionally correct design blocks
- Measure to identify verification holes and to show progress towards tape-out
- Create a constrained-random verification environment using SystemVerilog and Universal verification methodology (UVM)
Requirements For Silicon Design Verification Engineer, TPU, Google Cloud
- Bachelor's degree in Electrical Engineering or equivalent practical experience
- 4 years of experience with verification methodology such as Universal verification methodology (UVM)
- 2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc.
- Experience with SystemVerilog, SVA, and functional coverage
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