Silicon Design Verification Engineer

Google is a global technology company that develops and provides a wide range of internet-related services and products.
Backend
Entry-Level Software Engineer
In-Person
5,000+ Employees
1+ year of experience
AI · Enterprise SaaS

Description For Silicon Design Verification Engineer

Join Google's Technical Infrastructure team as a Silicon Design Verification Engineer for Google Cloud. In this role, you'll be part of a diverse team pushing boundaries and developing custom silicon solutions that power Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide, shaping the next generation of hardware experiences.

Your responsibilities will include collaborating with design and verification engineers on active projects, performing verification, and building efficient constrained-random verification environments. You'll be responsible for the entire verification life-cycle, from planning to test execution and collecting coverage.

As part of the Technical Infrastructure team, you'll work on the architecture that keeps Google's product portfolio running. This team develops and maintains data centers, builds next-generation Google platforms, and ensures networks are up and running for the best user experience.

Key qualifications include a Bachelor's degree in Electrical Engineering (or equivalent experience), 1 year of experience in IP design verification, and proficiency in SystemVerilog, SVA, and functional coverage. Experience with verification methodologies like UVM is also required.

Preferred qualifications include a Master's degree, experience with AI/ML accelerators, and familiarity with ASIC standard interfaces and memory system architecture. Join Google in delivering unparalleled performance, efficiency, and integration in hardware experiences!

Last updated 7 days ago

Responsibilities For Silicon Design Verification Engineer

  • Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools
  • Identify and write all types of coverage measures for stimulus and corner-cases
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Manage coverage measures to identify verification holes and show progress towards tape-out

Requirements For Silicon Design Verification Engineer

Java
  • Bachelor's degree in Electrical Engineering or equivalent practical experience
  • 1 year of experience in verification of IP designs (e.g., CPU, Peripherals, PMU, etc.)
  • Experience with SystemVerilog, SVA and functional coverage
  • Experience with verification methodology (e.g., UVM, OVM, VMM)

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