Silicon Networking Microarchitecture and RTL Lead
Description For Silicon Networking Microarchitecture and RTL Lead
This is a senior technical leadership position at Google Cloud focused on shaping the future of AI/ML hardware acceleration through TPU (Tensor Processing Unit) technology. The role combines deep technical expertise in silicon design with strategic leadership in developing custom silicon solutions for Google's most demanding AI/ML applications.
The position sits within Google's ML, Systems, & Cloud AI (MSCA) organization, which is responsible for the hardware, software, and infrastructure powering Google's services and Cloud offerings. The role involves working on cutting-edge ASICs used to accelerate and improve traffic efficiency in data centers, requiring collaboration across architecture, verification, power and performance, and physical design teams.
As a Silicon Networking Microarchitecture and RTL Lead, you'll be responsible for developing innovative micro-architectural solutions while balancing complexity, performance, power, and area considerations. The work directly impacts Google's TPU technology, which is crucial for AI/ML applications and powers Google Cloud's Vertex AI platform.
The role requires deep expertise in ASIC development, verification, and testing, with a focus on networking domain knowledge such as packet processing and congestion control. You'll work with cross-functional teams to drive feature development and ensure high-quality designs for next-generation data center accelerators.
This position offers the opportunity to work on technology that powers products used by billions of people worldwide, while being part of Google's commitment to security, efficiency, and reliability in hyperscale computing. The role combines technical leadership with hands-on development, making it ideal for someone who wants to impact the future of AI hardware acceleration while working with cutting-edge technology at scale.
Responsibilities For Silicon Networking Microarchitecture and RTL Lead
- Own microarchitecture and implementation of complex IPs and subsystems in the Networking domain
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop micro-architecture specifications
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Identify and lead power, performance, and area improvements for the domains owned
Requirements For Silicon Networking Microarchitecture and RTL Lead
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in micro-architecture and design of IPs and Subsystems in Networking domain such as Packet processing, bandwidth management, congestion control, etc.
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