Silicon Networking Microarchitecture and RTL Lead, Google Cloud
Description For Silicon Networking Microarchitecture and RTL Lead, Google Cloud
Google Cloud is seeking a Silicon Networking Microarchitecture and RTL Lead to shape the future of AI/ML hardware acceleration. This role focuses on developing cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll work on custom silicon solutions that accelerate and improve traffic efficiency in data centers.
The position involves collaborating with architecture, verification, power and performance, and physical design teams to deliver high-quality designs for next-generation data center accelerators. You'll be responsible for solving technical problems with innovative micro-architecture and practical logic solutions, while evaluating design options considering complexity, performance, power, and area constraints.
This is a unique opportunity to contribute to Google's global impact across software and hardware, including Google Cloud's Vertex AI platform, which brings Gemini models to enterprise customers. The role requires expertise in ASIC development, design verification, and deep knowledge of networking domain concepts such as packet processing and congestion control.
Working at Google's Bengaluru office, you'll be part of a team that prioritizes security, efficiency, and reliability while driving towards shaping the future of hyperscale computing. The position offers the chance to work on products used by billions of people worldwide and contribute to the innovation behind Google's next-generation infrastructure.
Responsibilities For Silicon Networking Microarchitecture and RTL Lead, Google Cloud
- Own microarchitecture and implementation of complex IPs and subsystems in the Networking domain
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop micro-architecture specifications
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Identify and lead power, performance, and area improvements for the domains owned
Requirements For Silicon Networking Microarchitecture and RTL Lead, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in micro-architecture and design of IPs and Subsystems in Networking domain such as Packet processing, bandwidth management, congestion control, etc.
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