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Silicon RTL Design Engineer, TPU, Google Cloud

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Description For Silicon RTL Design Engineer, TPU, Google Cloud

Join Google Cloud's TPU (Tensor Processing Unit) team as a Silicon RTL Design Engineer, where you'll be at the forefront of AI/ML hardware acceleration. This role offers the opportunity to shape the future of Google's custom silicon solutions that power their most demanding AI/ML applications. You'll be working on developing SoCs used to accelerate machine learning computation in data centers, solving technical problems with innovative logic solutions while considering performance, power, and area optimization.

As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll collaborate with cross-functional teams including architecture, verification, power and performance, and physical design to deliver high-quality designs for next-generation data center accelerators. Your work will directly impact Google's services and Cloud customers, contributing to the development of cutting-edge TPU technology.

The role requires expertise in ASIC/SoC development, micro-architecture design, and verification. You'll be responsible for implementing IPs and subsystems, working closely with Architecture and Design Leads, and driving improvements in power, performance, and area. This position offers the chance to work on technology that powers products used by billions of people worldwide, while being part of Google's mission to shape the future of hyperscale computing.

The ideal candidate should have strong experience with Verilog/SystemVerilog, ASIC design verification, and knowledge of processor design and bus architectures. Additional experience with programming languages like Python or C++ and understanding of high-performance computing will be valuable in this role.

Last updated 2 days ago

Responsibilities For Silicon RTL Design Engineer, TPU, Google Cloud

  • Own implementation of IPs and subsystems
  • Work with Architecture and Design Leads to understand micro-architecture specifications
  • Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
  • Identify and drive Power, Performance, and Area improvements for the domains

Requirements For Silicon RTL Design Engineer, TPU, Google Cloud

Python
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
  • 3 years of experience in ASIC/SoC development with Verilog/SystemVerilog
  • Experience in micro-architecture and design of IPs and subsystems
  • Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)

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