Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
Description For Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
Join Google Cloud's innovative team developing custom silicon solutions for machine learning acceleration in data centers. As a Senior RTL IP/Subsystem Engineer, you'll be part of the ML, Systems, & Cloud AI (MSCA) organization, working on cutting-edge ASIC development for next-generation data center accelerators. You'll collaborate with cross-functional teams on architecture, verification, and physical design to deliver high-performance, power-efficient solutions. The role combines hardware expertise with software integration, contributing to Google's global infrastructure that powers services used by billions. You'll work on microarchitecture design, implementation of IPs and subsystems, and drive improvements in power, performance, and area. The position offers the opportunity to shape the future of hyperscale computing and AI acceleration, working with technologies like TPUs and contributing to Google Cloud's Vertex AI platform.
Responsibilities For Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
- Own microarchitecture and implementation of Internet Protocol (IPs) and subsystems
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications
- Drive design methodology, libraries, debug, code review in coordination with other Internet Protocol (IPs) Design Verification (DV) teams and physical design teams
- Identify and drive power, performance and area of improvements
Requirements For Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL), or Chisel
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in micro-architecture and designing IPs and subsystems
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