Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
Description For Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
Join Google's innovative hardware team as a Silicon RTL IP/Subsystem Senior Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's direct-to-consumer products. This role focuses on developing ASICs used to accelerate machine learning computation in data centers, making it crucial for Google's next-generation data center accelerators.
As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll collaborate with diverse teams including architecture, verification, power and performance, and physical design to deliver high-quality solutions. Your work will directly impact Google's services (Search, YouTube, etc.) and Google Cloud, serving billions of users worldwide.
The position requires expertise in ASIC development, microarchitecture design, and system integration. You'll be responsible for solving complex technical problems, evaluating design options for optimal performance and power efficiency, and working with cutting-edge technology in machine learning acceleration.
This role offers the opportunity to shape the future of hyperscale computing, working on projects like Google Cloud's Vertex AI platform and contributing to the development of Gemini models for enterprise customers. The position combines hardware expertise with software integration, making it ideal for engineers passionate about pushing the boundaries of technology.
Working at Google means joining a team that prioritizes security, efficiency, and reliability while contributing to products that have global impact. The role offers the chance to work with world-class engineers and be part of Google's commitment to innovation in silicon design and machine learning acceleration.
Responsibilities For Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
- Own microarchitecture and implementation of Internet Protocol (IPs) and subsystems
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications
- Drive design methodology, libraries, debug, code review in coordination with other Internet Protocol (IPs) Design Verification (DV) teams and physical design teams
- Identify and drive power, performance and area of improvements
Requirements For Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL), or Chisel
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in micro-architecture and designing IPs and subsystems
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