Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
Description For Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
Join Google Cloud's innovative team developing custom silicon solutions for machine learning computation in data centers. As a Silicon RTL IP/Subsystem Senior Engineer, you'll be at the forefront of developing ASICs that accelerate machine learning computation, working within the ML, Systems, & Cloud AI (MSCA) organization.
Your role involves collaborating with cross-functional teams in architecture, verification, power and performance, and physical design to deliver next-generation data center accelerators. You'll tackle complex technical challenges in microarchitecture, evaluate design options considering complexity, performance, and power requirements, and contribute to Google's hyperscale computing future.
The position offers the opportunity to work on technology that powers Google's direct-to-consumer products and services used by billions worldwide. You'll be part of the team that manages hardware, software, and machine learning infrastructure for all Google services and Google Cloud, including cutting-edge projects like Google Cloud's Vertex AI platform.
This role combines hardware expertise with software integration, requiring strong technical skills in ASIC development, verification, and system architecture. You'll work in an environment that prioritizes security, efficiency, and reliability while pushing the boundaries of what's possible in hardware acceleration for machine learning.
The impact of your work will be felt across Google's global infrastructure, contributing to the company's leadership in AI and cloud computing. This is an excellent opportunity for experienced engineers passionate about hardware design and eager to shape the future of machine learning acceleration at scale.
Responsibilities For Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
- Own microarchitecture and implementation of Internet Protocol (IPs) and subsystems
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications
- Drive design methodology, libraries, debug, code review in coordination with other Internet Protocol (IPs) Design Verification (DV) teams and physical design teams
- Identify and drive power, performance and area of improvements
Requirements For Silicon RTL IP/Subsystem Senior Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in Application-specific integrated circuit (ASIC) development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL), or Chisel
- Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in micro-architecture and designing IPs and subsystems
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