Silicon Subsystems RTL Design Engineer, Google Cloud
Description For Silicon Subsystems RTL Design Engineer, Google Cloud
Join Google Cloud as a Silicon Subsystems RTL Design Engineer and shape the future of AI/ML hardware acceleration. This role focuses on developing cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of an innovative team developing custom silicon solutions for Google's TPU, contributing to products used by millions worldwide.
The position involves working on ASICs used to accelerate and improve data center traffic. You'll collaborate with various teams including architecture, verification, power and performance, and physical design to deliver next-generation data center accelerators. The role requires solving technical problems through innovative micro-architecture and practical logic solutions, while considering complexity, performance, power, and area trade-offs.
As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll work on infrastructure that supports all Google services and Google Cloud. The team prioritizes security, efficiency, and reliability while pushing the boundaries of hyperscale computing. This includes work on Google Cloud's Vertex AI, the leading AI platform for enterprise customers using Gemini models.
The ideal candidate will have strong experience in ASIC development, verification, and subsystem design. Knowledge of high-performance computing, low power design techniques, and familiarity with processor design and memory hierarchies is valuable. This is an opportunity to work at the forefront of AI hardware development while contributing to Google's global impact in both software and hardware domains.
Responsibilities For Silicon Subsystems RTL Design Engineer, Google Cloud
- Own microarchitecture and implementation of subsystems in the data center domain
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications
- Perform Quality check flows like Lint, CDC, RDC, VCLP
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Identify and drive power, performance and area improvements for the domains owned
Requirements For Silicon Subsystems RTL Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in micro-architecture and design of subsystems
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