Silicon Subsystems RTL Design Engineer, Google Cloud
Description For Silicon Subsystems RTL Design Engineer, Google Cloud
Join Google Cloud as a Silicon Subsystems RTL Design Engineer and shape the future of AI/ML hardware acceleration. You'll be working on cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. As part of the ML, Systems, & Cloud AI (MSCA) organization, you'll develop custom silicon solutions for next-generation data center accelerators.
Your role involves collaborating with architecture, verification, power and performance, and physical design teams to deliver quality designs. You'll solve technical challenges through innovative micro-architecture and logic solutions, while considering complexity, performance, power, and area trade-offs. The position requires expertise in ASIC development, design verification, and subsystem architecture.
The impact of your work will be significant, contributing to Google Cloud's Vertex AI platform and helping shape the future of hyperscale computing. You'll be part of a team that prioritizes security, efficiency, and reliability across all aspects of development, from TPU development to global network operations.
This is an excellent opportunity for experienced engineers passionate about hardware design and AI acceleration. You'll work with cutting-edge technology, collaborate with world-class teams, and contribute to products used by billions of people worldwide. The role offers the chance to work on complex technical challenges while driving innovation in the rapidly evolving field of AI hardware acceleration.
Responsibilities For Silicon Subsystems RTL Design Engineer, Google Cloud
- Own microarchitecture and implementation of subsystems in the data center domain
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications
- Perform Quality check flows like Lint, CDC, RDC, VCLP
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Identify and drive power, performance and area improvements for the domains owned
Requirements For Silicon Subsystems RTL Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in micro-architecture and design of subsystems
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