Silicon Subsystems RTL Design Engineer, Google Cloud
Description For Silicon Subsystems RTL Design Engineer, Google Cloud
Google is seeking a Silicon Subsystems RTL Design Engineer to join their Google Cloud team, focusing on shaping the future of AI/ML hardware acceleration. This role involves working on cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. The position is part of the ML, Systems, & Cloud AI (MSCA) organization, which is responsible for designing, implementing, and managing hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud.
The role offers an opportunity to drive innovation in custom silicon solutions that power Google's TPU future. You'll be contributing to products used by millions worldwide, leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As part of the team, you'll be developing ASICs used to accelerate and improve traffic in data centers, collaborating with various teams including architecture, verification, power and performance, and physical design to deliver quality designs for next-generation data center accelerators. The role requires solving technical problems with innovative micro-architecture and practical logic solutions, while evaluating design options considering complexity, performance, power, and area.
The position offers the opportunity to work on global-impact projects, from developing latest TPUs to running a global network, while contributing to the future of hyperscale computing. The team's work directly influences Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities For Silicon Subsystems RTL Design Engineer, Google Cloud
- Own microarchitecture and implementation of subsystems in the data center domain
- Work with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications
- Perform Quality check flows like Lint, CDC, RDC, VCLP
- Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams
- Identify and drive power, performance and area improvements for the domains owned
Requirements For Silicon Subsystems RTL Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 5 years of experience in ASIC development with Verilog/SystemVerilog, VHDL
- Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT)
- Experience in micro-architecture and design of subsystems
Benefits For Silicon Subsystems RTL Design Engineer, Google Cloud
- Comprehensive medical insurance
- Visa sponsorship available
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