SoC and IP Design Engineer, Google Cloud
Description For SoC and IP Design Engineer, Google Cloud
Join Google Cloud's ML, Systems, & Cloud AI (MSCA) organization as a SoC and IP Design Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's future. This role combines hardware expertise with cutting-edge technology, focusing on designing and implementing critical infrastructure for Google services and Cloud operations.
As a Senior Engineer, you'll work on complex System on Chip (SoC) architectures, utilizing your expertise in RTL design, verification, and optimization. The position requires strong technical skills in digital design principles, Verilog/SystemVerilog, and low-power design techniques. You'll be responsible for developing block-level design documents, performing RTL development, and ensuring quality through various verification processes.
The role offers the opportunity to work with state-of-the-art technology in a global team environment, contributing to projects that impact billions of users worldwide. You'll be part of an organization that prioritizes security, efficiency, and reliability while pushing the boundaries of hyperscale computing. The position involves collaboration with multi-disciplined teams across different locations, particularly in Tel Aviv and Haifa, Israel.
This is an excellent opportunity for experienced engineers who want to make a significant impact on Google's hardware infrastructure while working with cutting-edge technology in cloud computing and machine learning. The role combines technical depth with the chance to influence the future of Google's custom silicon solutions, making it an exciting position for those passionate about hardware design and innovation.
Responsibilities For SoC and IP Design Engineer, Google Cloud
- Define the System on a Chip (SoC)/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks
- Participate in synthesis, timing/power closure and Application-specific integrated circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SoC level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For SoC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or SystemVerilog
- Experience with reasoning synthesis techniques to optimize RTL code, performance and power with low-power design techniques
- Experience with design sign-off and quality tools (e.g., Lint, CDC, etc.)
- Experience in reasoning design and debug with Design Verification (DV)
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