SoC and IP Design Engineer, Google Cloud
Description For SoC and IP Design Engineer, Google Cloud
Join Google Cloud's innovative team as a SoC and IP Design Engineer, where you'll be part of the ML, Systems, & Cloud AI (MSCA) organization. This role combines hardware engineering expertise with cutting-edge cloud technology development. You'll work on designing and implementing custom silicon solutions that power Google's infrastructure and cloud services, including the development of TPUs and other specialized hardware.
The position involves working with state-of-the-art digital logic design, RTL development, and system-on-chip architecture. You'll be responsible for creating and optimizing hardware designs that drive Google's next-generation cloud computing capabilities. The role requires expertise in Verilog/System Verilog, logic synthesis, and verification techniques.
As part of Google's hardware engineering team, you'll collaborate with multi-disciplinary teams across different locations to develop innovative solutions for Google's cloud infrastructure. The work directly impacts billions of users through Google's services like Search, YouTube, and Google Cloud's Vertex AI platform.
This is an excellent opportunity for experienced hardware engineers who want to work at the intersection of cloud computing and custom silicon design. You'll be contributing to projects that push the boundaries of hyperscale computing while working with some of the industry's most advanced hardware technologies.
The position offers the chance to work on meaningful projects that shape the future of cloud computing infrastructure, with access to Google's vast resources and cutting-edge technology. You'll be part of a team that prioritizes security, efficiency, and reliability while driving innovation in hardware design for cloud computing applications.
Responsibilities For SoC and IP Design Engineer, Google Cloud
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks
- Participate in synthesis, timing/power closure, and Application-specific integrated circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC-level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For SoC and IP Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 3 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience in logic design and debug with Design Verification (DV)
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