SoC Design Engineer, Google Cloud
Description For SoC Design Engineer, Google Cloud
Google Cloud is seeking a talented SoC Design Engineer to join their Technical Infrastructure team. This role focuses on developing custom silicon solutions that power Google's direct-to-consumer products and data center accelerators. As a SoC Design Engineer, you'll be responsible for RTL design, architecture, and implementation of global communication busses, working with cross-functional teams to deliver high-performance ASIC designs.
The position requires strong expertise in RTL coding using Verilog/SystemVerilog and experience with industry-standard EDA tools. You'll work on challenging projects that directly impact millions of users worldwide, contributing to the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration.
The role offers an exciting opportunity to work with diverse teams, push technological boundaries, and shape the future of Google's hardware infrastructure. You'll be involved in mentoring other RTL designers, developing innovative methodologies, and creating efficient design environments for ASIC engineers.
Key responsibilities include developing system segmentation strategies, designing RTL architecture for optimized performance, and implementing complex digital blocks. You'll collaborate with various teams including Physical Design, Verification, Validation, and Firmware, ensuring successful project delivery at various milestones.
The position comes with competitive compensation including a base salary range of $150,000-$223,000, plus bonus, equity, and comprehensive benefits. This is an excellent opportunity for experienced engineers who want to make a significant impact in a leading technology company while working on cutting-edge hardware solutions.
Responsibilities For SoC Design Engineer, Google Cloud
- Develop strategies for system segmentation to enable programmatic assembly of custom solutions
- Design RTL architecture of system to allow for automated optimization of RTL performance, power, and area
- Provide mentorship and guidance for a team of RTL designers
- Design and implement RTL code for various digital blocks, including control logic, and on-chip data paths
- Contribute to the development and improvement of design flows, tools, and methodologies
Requirements For SoC Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of experience with RTL coding using Verilog/SystemVerilog
- Experience with industry-standard EDA tools for simulation, synthesis, and power analysis
- Experience architecting RTL solutions employing software based construction
- Experience with SOC implementation standards and interfaces (e.g., AXI)
- Experience with scripting languages (e.g., Tcl, Python or Perl)
- Understanding of digital design fundamentals
Benefits For SoC Design Engineer, Google Cloud
- Bonus
- Equity
- Benefits package
