SOC Design Engineer, Google Cloud
Description For SOC Design Engineer, Google Cloud
Join Google's ML, Systems, & Cloud AI (MSCA) organization as a SOC Design Engineer working on cutting-edge hardware solutions. In this role, you'll be part of a team that develops custom silicon solutions powering Google's direct-to-consumer products and cloud infrastructure. You'll work on System on Chip (SoC) design from conception to production, collaborating with cross-functional teams in architecture, software, verification, power, and timing.
The position requires expertise in digital design principles, RTL development, and hardware verification. You'll be responsible for defining SoC/block level design documents, implementing RTL code in Verilog/System Verilog, and ensuring optimal performance through synthesis and timing closure. The role involves working with state-of-the-art technologies in areas such as PCIe, UCIe, DDR, and ARM processors.
As part of Google's hardware team, you'll contribute to innovations that power billions of users worldwide. The MSCA organization is responsible for the hardware, software, and machine learning infrastructure supporting all Google services and Google Cloud. This includes developing TPUs and managing global network infrastructure, with a focus on security, efficiency, and reliability.
This is an excellent opportunity for a skilled hardware engineer to work on challenging projects at scale, collaborate with world-class teams, and make a significant impact on Google's hardware ecosystem. The role offers exposure to cutting-edge technology and the chance to shape the future of hyperscale computing while working on products that serve billions of users globally.
Responsibilities For SOC Design Engineer, Google Cloud
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks
- Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up
- Participate in test plan and coverage analysis of the block and SOC-level verification
- Communicate and work with multi-disciplined and multi-site teams
Requirements For SOC Design Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 3 years of experience with digital reasoning design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog
- Experience with reasoning synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques
- Experience in reasoning design and debug with Design Verification (DV)
