SoC Design for Testing Engineer, Google Cloud
Description For SoC Design for Testing Engineer, Google Cloud
Google Cloud is seeking a System on a Chip (SoC) Design for Testing (DFT) Engineer to join their team developing custom silicon solutions. This role is crucial in defining, implementing, and deploying advanced DFT methodologies for highly digital or mixed-signal chips and IPs. The position involves working on cutting-edge hardware that powers Google's direct-to-consumer products, focusing on silicon test strategies, DFT architecture, and CPU specifications.
As part of Google's Technical Infrastructure team, you'll be responsible for the architecture that keeps Google's vast product portfolio running. The role combines technical expertise in DFT methodologies with hands-on implementation of test solutions. You'll work on reducing test costs, increasing production quality, and enhancing yield while collaborating with test engineers for post-silicon activities.
The ideal candidate should have a strong background in electrical engineering with specific expertise in Design For Test methodologies. Experience with ASIC DFT synthesis, simulation, and verification flow is essential. The role offers the opportunity to work on innovative hardware solutions that impact millions of users worldwide while being part of a team that pushes the boundaries of technological advancement.
This position is perfect for someone who enjoys working with complex systems, has a strong attention to detail, and wants to contribute to the next generation of Google's hardware experiences. The role offers the chance to work with cutting-edge technology while being part of a team that values innovation and technical excellence.
Responsibilities For SoC Design for Testing Engineer, Google Cloud
- Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG)
- Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins
Requirements For SoC Design for Testing Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience
- 2 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools
- Experience with ASIC DFT synthesis, simulation, and verification flow
- Experience using Electronic Design Automation (EDA) test tools (e.g., Spyglass, Tessent, etc.)
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