SoC Design for Testing Engineer, Google Cloud
Description For SoC Design for Testing Engineer, Google Cloud
Google Cloud is seeking a System on a Chip (SoC) Design for Testing (DFT) Engineer to join their team in developing custom silicon solutions. This role is part of the Technical Infrastructure team, which is responsible for building and maintaining Google's data centers and platforms. The position focuses on defining, implementing, and deploying advanced DFT methodologies for highly digital or mixed-signal chips or IPs.
As a DFT Engineer, you will be responsible for defining silicon test strategies, DFT architecture, and creating DFT specifications for CPUs. The role involves designing, inserting, and verifying DFT logic, as well as working closely with test engineers for post-silicon activities. Your work will directly impact the reduction of test costs, improvement of production quality, and enhancement of yield.
The position offers the opportunity to work on cutting-edge technology that powers Google's direct-to-consumer products, contributing to innovations that are used by millions of users worldwide. You'll be part of a team that pushes boundaries in hardware development, focusing on delivering unparalleled performance, efficiency, and integration.
The role requires a strong background in electrical engineering and DFT methodologies, with hands-on experience in ASIC DFT synthesis and verification. You'll work with industry-standard tools and be involved in various aspects of the SoC development cycle, from architecture definition to silicon bring-up.
This is an excellent opportunity for someone passionate about hardware design and testing, offering the chance to work on complex systems while being part of Google's innovative Technical Infrastructure team. The position provides exposure to cutting-edge technology and the opportunity to shape the future of Google's hardware products.
Responsibilities For SoC Design for Testing Engineer, Google Cloud
- Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG)
- Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins
Requirements For SoC Design for Testing Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience
- 2 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools
- Experience with ASIC DFT synthesis, simulation, and verification flow
- Experience using Electronic Design Automation (EDA) test tools (e.g., Spyglass, Tessent, etc.)
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