SoC Design for Testing Engineer, Google Cloud
Description For SoC Design for Testing Engineer, Google Cloud
Google Cloud is seeking a System on a Chip (SoC) Design for Testing (DFT) Engineer to join their team in developing custom silicon solutions. This role is crucial in defining, implementing, and deploying advanced DFT methodologies for highly digital or mixed-signal chips or IPs. As part of Google's Technical Infrastructure team, you'll be responsible for the architecture that powers Google's extensive product portfolio.
The position involves working on cutting-edge hardware development, focusing on silicon test strategies, DFT architecture, and CPU specifications. You'll be hands-on with designing, inserting, and verifying DFT logic, while also collaborating with test engineers for post-silicon work. Your work will directly impact production quality, test cost reduction, and yield enhancement.
This is an excellent opportunity for someone with a strong background in electrical engineering and DFT methodologies. You'll be working with state-of-the-art tools and technologies, contributing to the innovation behind products used by millions worldwide. The role offers the chance to work with advanced silicon development cycles, including silicon bring-up and debug activities.
The position requires expertise in ASIC DFT synthesis, simulation, and verification flow, along with proficiency in Electronic Design Automation (EDA) test tools. You'll be part of a team that pushes boundaries and develops solutions that power the future of Google's direct-to-consumer products, making this an exciting opportunity for those passionate about hardware innovation and testing methodologies.
Responsibilities For SoC Design for Testing Engineer, Google Cloud
- Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG)
- Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins
Requirements For SoC Design for Testing Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience
- 2 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools
- Experience with ASIC DFT synthesis, simulation, and verification flow
- Experience using Electronic Design Automation (EDA) test tools (e.g., Spyglass, Tessent, etc.)
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