SoC Design for Testing Engineer, Google Cloud
Description For SoC Design for Testing Engineer, Google Cloud
Google Cloud is seeking a System on a Chip (SoC) Design for Testing (DFT) Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position involves defining, implementing, and deploying advanced DFT methodologies for highly digital or mixed-signal chips or IPs. The engineer will be responsible for defining silicon test strategies, DFT architecture, and creating DFT specifications for CPUs.
The role is part of Google's Technical Infrastructure team, which builds and maintains the architecture behind all of Google's user-facing products. The team is responsible for developing and maintaining data centers and building next-generation Google platforms. The position requires expertise in DFT methodologies, verification, and industry-standard tools, with a focus on reducing test cost, increasing production quality, and enhancing yield.
Key responsibilities include developing DFT strategy and architecture, implementing test design rule checks, inserting DFT logic and various test-related components, and documenting architecture and test sequences. The ideal candidate should have a strong background in Electrical Engineering with experience in fault modeling, IP integration, and working with ATE engineers on silicon bring-up and debug activities.
This is an excellent opportunity for someone passionate about hardware engineering and testing, offering the chance to work on cutting-edge technology that impacts millions of users worldwide. The position offers the opportunity to work with advanced testing methodologies and contribute to the development of next-generation hardware experiences, focusing on unparalleled performance, efficiency, and integration.
Responsibilities For SoC Design for Testing Engineer, Google Cloud
- Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG)
- Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins
Requirements For SoC Design for Testing Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience
- 2 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools
- Experience with ASIC DFT synthesis, simulation, and verification flow
- Experience using Electronic Design Automation (EDA) test tools (e.g., Spyglass, Tessent, etc.)
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