SoC Design for Testing Engineer, Google Cloud
Description For SoC Design for Testing Engineer, Google Cloud
Join Google Cloud's Technical Infrastructure team as a SoC Design for Testing Engineer, where you'll be at the forefront of developing custom silicon solutions that power Google's future direct-to-consumer products. This role combines hardware expertise with software testing methodologies to ensure the reliability and quality of Google's custom chips.
As a DFT Engineer, you'll be responsible for defining, implementing, and deploying advanced Design for Testing methodologies for highly digital or mixed-signal chips and IPs. You'll work on defining silicon test strategies, DFT architecture, and creating DFT specifications for CPUs. The role involves designing, inserting, and verifying DFT logic, while also preparing for post-silicon testing and collaborating with test engineers for debugging.
The position is part of Google's Technical Infrastructure team, which builds and maintains the architecture behind Google's vast product portfolio. The team takes pride in being "engineers' engineers" and isn't afraid to dive deep into complex technical challenges. Your work will directly impact the performance, efficiency, and integration of Google's hardware experiences, ultimately serving millions of users worldwide.
This role offers the opportunity to work with cutting-edge technology in silicon design and testing, while collaborating with world-class engineers. You'll be responsible for critical aspects of chip development, including reducing test costs, increasing production quality, and enhancing yield. The position requires a strong background in electrical engineering and DFT methodologies, with opportunities to work on next-generation hardware solutions.
Join a team that pushes boundaries and shapes the future of Google's hardware infrastructure, while working in either Haifa or Tel Aviv, Israel. This role offers the perfect blend of technical challenge and meaningful impact, making it an ideal opportunity for someone passionate about hardware design and testing.
Responsibilities For SoC Design for Testing Engineer, Google Cloud
- Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG)
- Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins
Requirements For SoC Design for Testing Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience
- 2 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools
- Experience with ASIC DFT synthesis, simulation, and verification flow
- Experience using Electronic Design Automation (EDA) test tools (e.g., Spyglass, Tessent, etc.)
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