SoC DFT Engineer, Google Cloud
Description For SoC DFT Engineer, Google Cloud
Google Cloud is seeking a System on a Chip (SoC) Design for Test (DFT) Engineer to join their ML, Systems, & Cloud AI (MSCA) organization. This role is crucial in defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. The position involves working on custom silicon solutions that power Google's direct-to-consumer products, contributing to hardware innovations used by millions worldwide.
The role requires expertise in silicon test strategies, DFT architecture, and creating DFT specifications for next-generation SoCs. You'll be responsible for designing, inserting, and verifying DFT logic, as well as collaborating with test engineers for post-silicon work and debugging.
As part of the MSCA organization, you'll be working on infrastructure that supports all Google services (Search, YouTube, etc.) and Google Cloud. The team prioritizes security, efficiency, and reliability across all projects, from developing TPUs to managing global networks. This position offers the opportunity to shape the future of hyperscale computing and work with cutting-edge technologies like Google Cloud's Vertex AI platform.
The ideal candidate should have strong experience in DFT methodologies, ASIC verification, and industry-standard tools. Knowledge of memory built-in self-test, test access points, and silicon bring-up is highly valued. This role offers the chance to work on innovative hardware solutions while being part of a team that drives Google's technological advancement in cloud computing and AI infrastructure.
Responsibilities For SoC DFT Engineer, Google Cloud
- Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT)
- Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins
Requirements For SoC DFT Engineer, Google Cloud
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience
- 3 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools
- Experience with ASIC DFT synthesis, simulation, and verification flow
- Experience in DFT specification, definition, architecture, and insertion
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