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SoC Interface Architect, Silicon

Google develops custom silicon solutions that power direct-to-consumer products, combining AI, Software, and Hardware to create helpful experiences.
Embedded
Mid-Level Software Engineer
In-Person
5,000+ Employees
3+ years of experience
AI · Consumer · Hardware

Description For SoC Interface Architect, Silicon

Google's Devices & Services team is seeking a SoC Interface Architect to join their silicon development efforts. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products, combining the best of Google AI, Software, and Hardware to create innovative user experiences.

The position involves architecting and designing low-speed interfaces and GPIO systems for Google's hardware products. You'll be responsible for defining requirements, creating architecture specifications, and programming guides while analyzing critical trade-offs in performance, power, area, and cost. The role requires expertise in protocols like I2C, UART, and SPI, with preferred experience in I2S, JTAG, TDM, PDM, SoundWire, and SPMI.

As part of Google's mission to organize the world's information and make it universally accessible, you'll work with a team that pushes boundaries in hardware development. The position offers the opportunity to shape next-generation hardware experiences, delivering unparalleled performance, efficiency, and integration.

The ideal candidate will have strong technical expertise in electrical engineering, particularly in interface protocols and GPIO circuit design. You'll collaborate with system teams, lead interface development lifecycles, and contribute to Google's innovative hardware ecosystem. This role combines technical leadership with hands-on architecture work, making it perfect for someone passionate about silicon design and system architecture.

Last updated 3 days ago

Responsibilities For SoC Interface Architect, Silicon

  • Define the requirements and author architecture specifications and the programming guides
  • Analyze performance, power, area, and cost trade-offs
  • Perform Third-Party IP phones (3PIP) selection of low speed interface IPs and GPIO IPs
  • Define and maintain SoC input/output (IO) map collaborating with the system team
  • Lead and support throughout the life cycle of low speed interfaces development

Requirements For SoC Interface Architect, Silicon

  • Bachelor's degree in Electrical Engineering or equivalent practical experience
  • 3 years of experience in architecture, microarchitecture, design, or physical design of low speed interfaces or GPIO
  • Experience in protocols such as I2C, UART, SPI

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