SoC RTL Design Engineer
Description For SoC RTL Design Engineer
Join Google's ML, Systems, & Cloud AI (MSCA) organization as a SoC RTL Design Engineer, where you'll be part of a team developing custom silicon solutions that power Google's direct-to-consumer products. This role focuses on SoC-level RTL design for data center accelerators, with emphasis on management and control subsystems.
You'll be responsible for designing Register-Transfer Level (RTL) IP, developing infrastructure and methodology for SoCs, including clocking, reset, error handling, debug, chip management, and SOC chassis. The position requires strong cross-functional collaboration with software and system hardware teams, making it ideal for someone with both technical expertise and communication skills.
The role offers competitive compensation ($156,000-$229,000 + bonus + equity + benefits) and the opportunity to work on cutting-edge technology that impacts billions of users worldwide. You'll be part of Google's broader mission in shaping the future of hyperscale computing, working on projects that include TPUs and global network infrastructure.
Key responsibilities include creating microarchitecture specifications, developing SystemVerilog RTL, collaborating with Architecture and Power teams, and working with design validation teams. The ideal candidate will have at least 3 years of RTL coding experience, strong understanding of digital design fundamentals, and preferably experience with PCIe design and common library RTL modules.
This position offers the chance to work at Google's Sunnyvale location, contributing to projects that directly impact Google's services and Cloud infrastructure. You'll be part of an organization that prioritizes security, efficiency, and reliability while pushing the boundaries of what's possible in hardware and software integration.
Responsibilities For SoC RTL Design Engineer
- Work separately to create and review management and control subsystem's design microarchitecture specifications
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines
- Work with Architecture and Power teams to evaluate features and their impact
- Work with design validation (DV) teams to create test plans to verify, and debug design RTL
- Work with physical design teams to ensure design meets physical requirements and timing closure
Requirements For SoC RTL Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 3 years of experience with RTL coding using Verilog/SystemVerilog
- Experience with industry-standard EDA tools for simulation, synthesis and power analysis
Benefits For SoC RTL Design Engineer
- bonus
- equity
- benefits
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