SoC RTL Security Design Engineer
Description For SoC RTL Security Design Engineer
Join Google's ML, Systems, & Cloud AI (MSCA) organization as a SoC RTL Security Design Engineer, where you'll be part of a team developing custom silicon solutions for Google's direct-to-consumer products. This role focuses on SoC-level RTL design for data center accelerators, with emphasis on security subsystems and management control. You'll be working on designing RTL IP, developing infrastructure, and collaborating with software and hardware teams.
The position requires expertise in RTL coding, security design, and system architecture. You'll be responsible for creating microarchitecture specifications, implementing logic using SystemVerilog, and working closely with validation and physical design teams. The role combines technical depth in hardware security with broad system-level understanding.
Google offers a competitive compensation package, including a base salary range of $156,000-$229,000, plus bonus, equity, and comprehensive benefits. The company prioritizes security, efficiency, and reliability across all projects, from TPU development to global network management. This is an opportunity to shape the future of hyperscale computing and contribute to Google's global impact across software and hardware platforms.
The ideal candidate will have strong experience in ASIC design, security implementation, and cross-functional collaboration. You'll be working in Sunnyvale, CA, contributing to projects that power Google's services used by billions of people worldwide. This role offers the chance to work on cutting-edge technology while being part of a team that pushes boundaries in hardware innovation.
Responsibilities For SoC RTL Security Design Engineer
- Create and review the security subsystem's design microarchitecture specifications
- Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines
- Work with architecture and power teams to evaluate security features and their impact
- Work with design validation (DV) teams to create test plans to verify and debug RTL designs
- Work with physical design teams to ensure design meets physical requirements and timing closure
Requirements For SoC RTL Security Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
- 8 years of experience with RTL coding using Verilog/SystemVerilog
- Experience with industry-standard EDA tools for simulation, synthesis and power analysis
Benefits For SoC RTL Security Design Engineer
- Medical Insurance
- Equity
- 401k
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