Static Timing Analysis Engineer, FullChip/ASIC Implementation
Description For Static Timing Analysis Engineer, FullChip/ASIC Implementation
Google is seeking a Static Timing Analysis Engineer to join their hardware team focusing on custom silicon solutions for direct-to-consumer products. This role combines advanced technical expertise in ASIC design and timing analysis with the opportunity to shape next-generation hardware experiences. The position requires deep knowledge of System-on-Chip (SoC) timing analysis, clock tree implementation, and signoff processes. The ideal candidate will have extensive experience with static timing tools and silicon timing closure at advanced technology nodes. This role offers the chance to work on cutting-edge hardware projects that directly impact millions of users worldwide, while being part of Google's innovative hardware development team. The position comes with competitive compensation including base salary, bonus, equity, and comprehensive benefits. The role involves collaboration with cross-functional teams to deliver high-performance, efficient silicon solutions that power Google's future hardware products. This is an excellent opportunity for experienced engineers looking to make a significant impact in a leading technology company while working on challenging and meaningful projects.
Responsibilities For Static Timing Analysis Engineer, FullChip/ASIC Implementation
- Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis
- Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs
- Drive clock tree planning and implementation for SoCs to achieve best energy, performance and area
- Oversee full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation, and final timing signoff for SoC's
Requirements For Static Timing Analysis Engineer, FullChip/ASIC Implementation
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 5 years of technical experience in silicon timing closure and chip integration
- Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation
- Experience in one or more static timing tools (e.g., PrimeTime, Tempus)
Benefits For Static Timing Analysis Engineer, FullChip/ASIC Implementation
- Medical Insurance
- Equity
- 401k
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