Tensor SOC Performance DV Engineer
Description For Tensor SOC Performance DV Engineer
Google is seeking a Tensor SOC Performance DV Engineer to join their hardware team, focusing on developing custom silicon solutions that power Google's direct-to-consumer products. This role combines hardware engineering with performance optimization, requiring expertise in SOC architecture and verification. The position involves working with cutting-edge technology at one of the world's leading tech companies, specifically on the Tensor chip that powers Google's devices.
The role requires a strong background in hardware verification, particularly with SystemVerilog and UVM, along with experience in SOC performance analysis and architecture. You'll be working on pre-silicon performance simulation and correlating results with actual silicon measurements, which is crucial for ensuring the optimal performance of Google's custom chips.
This is an excellent opportunity for someone passionate about hardware engineering and performance optimization to work on products that impact millions of users worldwide. You'll be collaborating with various teams, including system architects, CPU/GPU/TPU designers, and software experts, making it an ideal position for someone who enjoys cross-functional work.
The position offers the chance to work on next-generation hardware experiences at Google's Bengaluru office, contributing to the company's mission of organizing the world's information and making it universally accessible. You'll be part of a team that combines Google's strengths in AI, Software, and Hardware to create innovative solutions.
For the right candidate, this role offers the opportunity to work on challenging technical problems, contribute to architectural decisions, and help shape the future of Google's custom silicon solutions. The position requires both technical depth in hardware engineering and the ability to communicate complex technical concepts effectively.
Responsibilities For Tensor SOC Performance DV Engineer
- Develop simulators and architectural models of Google's Tensor System on a Chip (SOC)
- Collaborate with system architects, SoC and CPU/GPU/TPU architects/designers, and software and application experts
- Participate in architectural and design evaluation of Tensor SOC features studies
- Perform pre-silicon performance simulation and correlate with pre and post-silicon measurements
- Communicate analysis results qualitatively and quantitatively
Requirements For Tensor SOC Performance DV Engineer
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience
- 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog
- Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level
- Experience in performance and latency architecture for an ARM based SOC
- Experience in mobile SOC performance model development, performance analysis, and workload characterization
- Experience performance measurement and debugging in an emulation environment
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