TPU Microarchitecture Design Lead
Description For TPU Microarchitecture Design Lead
Google is seeking a TPU Microarchitecture Design Lead to join their team developing next-generation technologies for machine learning acceleration. This role combines hardware engineering and machine learning expertise to create cutting-edge TPU (Tensor Processing Unit) architectures. The position involves leading technical teams in designing and implementing machine learning processors and accelerators for Google's Silicon SoCs.
The ideal candidate will have extensive experience in RTL design, microarchitecture development, and team leadership. They will be responsible for defining architectural details, overseeing RTL development, and ensuring successful delivery of machine learning IPs. The role requires deep expertise in hardware design, including experience with ARM-based SoCs, interconnects, and ASIC methodology.
This is an opportunity to work at the intersection of AI and hardware, developing processors that power Google's machine learning infrastructure. The position offers competitive compensation including base salary, bonus, equity, and comprehensive benefits. The role is based in either Mountain View or San Diego, California, working with Google's Silicon team to push the boundaries of AI acceleration hardware.
The successful candidate will drive technical leadership for machine learning hardware development, collaborate across teams, and contribute to Google's mission of making information universally accessible through advanced AI technologies. This is a chance to shape the future of machine learning hardware while working with industry-leading experts in both AI and silicon development.
Responsibilities For TPU Microarchitecture Design Lead
- Technically lead a project team that delivers Machine Learning IPs for Google Silicon SoCs
- Define microarchitecture details for Machine learning processors and accelerators along with specification of data flows and integration requirements for Subsystem Development
- Oversee RTL development, and debug functional/performance simulations
- Meet schedule commitments and provide support to customers
- Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up
Requirements For TPU Microarchitecture Design Lead
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience
- 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture
- 4 years of experience in leading IP/SoC design teams
- Experience with ARM-based SoCs, interconnects, and ASIC methodology
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