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Design Verification Engineer

Intel Corporation is a global technology leader in semiconductor design and manufacturing.
$139,710 - $197,230
Backend
Senior Software Engineer
Hybrid
5,000+ Employees
6+ years of experience
Enterprise SaaS · Hardware

Description For Design Verification Engineer

Intel Corporation is seeking a talented Design Verification Engineer to join their team in Santa Clara, California. This role offers an exciting opportunity to work at the forefront of semiconductor technology, focusing on functional logic verification of integrated subsystems.

The position requires a strong background in verification engineering, with at least 6 years of experience in Design Verification at IP, SubSystem, or SOC level. You'll be working with cutting-edge technology, developing and executing verification plans, and ensuring design specifications are met through comprehensive testing and debugging.

As a Design Verification Engineer, you'll be responsible for defining and developing scalable verification plans, creating test benches, and maintaining verification environments. You'll work closely with cross-functional teams, including SoC architects, microarchitects, and RTL developers, to improve verification of complex architectural features.

The role offers competitive compensation, with a salary range of $139,710 to $197,230, along with comprehensive benefits including stock options, bonuses, health coverage, and retirement benefits. Intel provides a hybrid work model, allowing flexibility between on-site and remote work.

This is an excellent opportunity for someone passionate about verification engineering, with strong skills in SystemVerilog and UVM methodology. You'll be part of Intel's Network & Edge Group, working on critical products that drive technology leadership in the industry.

The ideal candidate will be self-driven, capable of handling block verification independently, and have excellent communication skills for collaboration with various teams. Experience with Networking-IP (TCP-IP/ROCE/RDMA) is a plus.

Intel offers a supportive work environment, opportunities for professional growth, and the chance to work on innovative technologies that shape the future of computing. Join Intel's team and be part of developing the next generation of semiconductor technology while working with industry-leading professionals in a collaborative environment.

Last updated a day ago

Responsibilities For Design Verification Engineer

  • Perform functional logic verification of integrated SubSystem
  • Define and develop verification plans, test benches, and verification environments
  • Execute verification plans and run system simulation models
  • Debug issues in the presilicon environment
  • Collaborate with SoC architects, microarchitects, and other teams
  • Document test plans and drive technical reviews
  • Incorporate security activities within test plans
  • Maintain and improve functional verification infrastructure
  • Work independently with cross-functional teams

Requirements For Design Verification Engineer

  • Bachelors or MS in Electrical engineering or Computer science
  • 6+ years in Design Verification at IP, SubSystem or SOC level
  • 2+ years of experience in System Verilog and UVM methodology
  • Experience in Networking-IP (TCP-IP/ROCE/RDMA) preferred

Benefits For Design Verification Engineer

Medical Insurance
401k
  • Competitive pay
  • Stock options
  • Bonuses
  • Health benefits
  • Retirement benefits
  • Vacation time

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