ASIC, Design Verification Engineer
Description For ASIC, Design Verification Engineer
Meta is seeking an experienced ASIC Design Verification Engineer to join their team in Austin, TX. This role is crucial in ensuring the quality and reliability of Meta's hardware designs, particularly as the company moves into immersive technologies like AR and VR.
The position offers a competitive compensation package ranging from $191,902 to $234,520 per year, plus bonus, equity, and comprehensive benefits. As a Design Verification Engineer, you'll be responsible for developing functional tests, implementing verification plans, and working with cross-functional teams to ensure the highest design quality.
The ideal candidate will have at least 3 years of experience in ASIC verification, with strong expertise in SystemVerilog/UVM methodology or C/C++ based verification. You'll need a proven track record of successful ASIC development cycles and proficiency in various EDA tools and scripting languages.
At Meta, you'll be part of a company that's shaping the future of social technology, moving beyond traditional screens toward immersive experiences. You'll work with cutting-edge hardware designs and collaborate with talented teams across Design, Model, Emulation, and Silicon validation.
The role offers an opportunity to work on challenging technical problems while contributing to Meta's mission of connecting people and building communities. You'll be supported by a strong engineering culture and have access to state-of-the-art tools and resources.
Meta provides a comprehensive benefits package including medical, dental, and vision insurance, along with equity opportunities. The company is committed to fostering an inclusive workplace and provides reasonable accommodations for qualified individuals with disabilities.
If you're passionate about hardware verification, have a strong technical background, and want to be part of building the next evolution in social technology, this role offers an exciting opportunity to make a significant impact at one of the world's leading technology companies.
Responsibilities For ASIC, Design Verification Engineer
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Define and implement IP/SoC verification plans, build verifications test benches
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams
Requirements For ASIC, Design Verification Engineer
- Bachelor's degree in Computer Science, Computer Software, Computer Engineering, Electrical and Computer Engineering, Applied Sciences, Mathematics, Physics, or related field
- 3 years of experience with System Verilog/UVM methodology or C/C++ based verification
- Track record of 'first-pass success' in ASIC development cycles
- Experience with Block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience with EDA tools and scripting (Python, TCL, Perl, Shell)
- Experience in architecting and implementing Design Verification infrastructure
Benefits For ASIC, Design Verification Engineer
- Medical Insurance
- Dental Insurance
- Vision Insurance
- Equity
