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ASIC DV Engineer, Simulation Acceleration and Hybrid Verification

Meta builds technologies that help people connect, find communities, and grow businesses, including apps like Facebook, Messenger, Instagram, and WhatsApp.
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Staff Software Engineer
In-Person
5,000+ Employees
8+ years of experience
AI · Enterprise SaaS

Description For ASIC DV Engineer, Simulation Acceleration and Hybrid Verification

Meta is seeking an experienced ASIC Verification Engineer to join their Infrastructure organization, focusing on Simulation Acceleration using Emulation and Hybrid Platforms. This role is crucial for developing IP and System On Chip (SoC) solutions for Meta's data center applications. As a Design Verification Engineer, you'll be part of an elite team working on innovative ASIC solutions, responsible for verification closure from test-planning to hybrid test bench development. The position offers extensive opportunities to collaborate with full-stack software, hardware, ASIC Design, Emulation, and Post-Silicon teams to achieve first-pass silicon success.

The role requires deep expertise in Simulation Acceleration and Hybrid Verification Methodology, working closely with Architecture and Design teams to develop and implement comprehensive test plans. You'll be responsible for defining verification scope, creating environments, and ensuring closure of use case scenarios and performance metrics at both Cluster and SoC levels. The position demands strong debugging skills and the ability to resolve functional failures while partnering with the Design team.

Key aspects of the role include developing and driving continuous Hybrid Verification improvements, building scalable verification environments, and evaluating cutting-edge solutions for Hybrid Verification and Simulation Acceleration. The ideal candidate will have extensive experience with platforms like Zebu, Palladium, and Veloce, along with proficiency in languages such as Verilog, SystemVerilog, UVM, and C/C++. The role also involves mentoring team members and providing training on Hybrid Verification Methodology.

This position at Meta offers the opportunity to work on cutting-edge technology in data center applications, including Video, AI/ML, and Networking designs. The role combines technical expertise with leadership responsibilities, making it ideal for experienced professionals looking to make a significant impact in hardware verification at one of the world's leading technology companies.

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Responsibilities For ASIC DV Engineer, Simulation Acceleration and Hybrid Verification

  • Propose, implement and promote Simulation Acceleration and Hybrid Verification Methodology
  • Work with Architecture and Design teams on functional test plans
  • Define Verification scope and create environment
  • Debug and resolve functional failures
  • Develop Hybrid Verification improvements
  • Build reusable environments for Hybrid Verification
  • Provide training and mentoring for internal teams

Requirements For ASIC DV Engineer, Simulation Acceleration and Hybrid Verification

Python
Linux
  • Bachelor's degree in Computer Science, Computer Engineering, or relevant field
  • 8+ years of relevant experience
  • Track record of 'first-pass success' in ASIC development
  • Experience in Verilog, SystemVerilog, UVM, C/C++, Python based verification
  • Experience with Zebu, Palladium, Veloce HW platforms
  • Proficiency in scripting languages (Python, Perl, TCL)
  • Experience in Cluster and SoC level verification
  • Demonstrated collaboration with cross functional teams

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