Principal Engineer, Mask Layout

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is seeking a Principal Engineer, Mask Layout to join their team. This role is crucial in defining and delivering operational measures of success for hardware manufacturing, improving planning processes, quality, delivery, scale, and sustainability related to Microsoft cloud hardware. The ideal candidate will have extensive experience in custom SRAM Memory Layout and proficiency with Calibre and Cadence tools.

Key responsibilities include:

• Leading detailed layout of SRAM cells, memory arrays, and peripheral circuits
• Ensuring adherence to design rule checks, layout vs. schematic checks, and addressing DFM and antenna effects
• Optimizing layout for performance, power, and area
• Collaborating with circuit designers and other layout designers
• Preparing layouts for final tape-out
• Providing technical leadership and mentorship to layout engineers

Required qualifications:

• 9+ years of related technical engineering experience
• 9+ years of experience in custom SRAM Memory Layout
• 9+ years of experience using Calibre and Cadence tools

Preferred qualifications include experience with Ansys Totem, deep knowledge of custom digital layout design, expertise in Python, SKILL, or TCL scripting and C programming, and proficiency with 5nm and/or 3nm technology nodes.

This role offers a competitive salary range of USD $137,600 - $267,000 per year (higher in San Francisco and New York City areas), along with comprehensive benefits including industry-leading healthcare, educational resources, and generous time off.

Join Microsoft's innovative team and contribute to powering the "Intelligent Cloud" mission while working on cutting-edge technology in a collaborative and dynamic environment.