Senior Design Verification Engineer
Description For Senior Design Verification Engineer
NVIDIA is seeking a Senior Design Verification Engineer to join their MMPLEX team in Shanghai, which consists of over 300 members. The team focuses on delivering cutting-edge IP solutions across NVIDIA's product lines including datacenter, GeForce, automotive, networking, and more. Their IPs cover technologies like micro-processors, security, DL/CV accelerators, display, video encoder/decoder, and image processors.
As a Verification Engineer, you'll be instrumental in ensuring the quality and functionality of hardware IPs. The role involves sophisticated verification methodologies, working with UVM, and handling complex testing environments. You'll be responsible for building and maintaining test benches, analyzing coverage results, and working closely with design engineers to improve product quality.
The ideal candidate should have strong technical expertise in verification methodologies, Verilog, and HVL, with either a BS with 5+ years experience or MS with 3+ years experience. Programming skills in languages like Perl, C++, Python, or Ruby are highly valued. The position offers competitive compensation and benefits, making it an attractive opportunity for experienced verification engineers looking to work on cutting-edge technology at a global leader in accelerated computing.
NVIDIA is known for its inclusive work environment and commitment to diversity, making it one of the most desirable employers in the technology sector. The role offers the chance to work on innovative projects that are transforming major industries through AI and digital twins technology.
Responsibilities For Senior Design Verification Engineer
- Research verification methodology to improve automation and productivity
- Read IAS and design specs to understand requirements and build test plans
- Build block/IP testbench based on UVM methodology
- Build test run and regression flow
- Triage failures and help root cause bugs
- Monitor metrics like passing rate and functional coverage
- Perform SOC verification on full chip test environment
- Analyze functional/code coverage results and identify coverage holes
- Deploy advanced verification methodology for SOC/IP
Requirements For Senior Design Verification Engineer
- BS/MS in electrical/computer engineering or equivalent experience
- 3+ years (MS) or 5+ years (BS) working experience
- Familiar with advanced verification methodology, tools and flow
- Experience with verification flow including testplan, coverage model, testbench
- Deep understanding of Verilog and HVL (High-level Verification Language)
Benefits For Senior Design Verification Engineer
- Competitive salaries
- Generous benefits package
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